JPH0579176B2 - - Google Patents

Info

Publication number
JPH0579176B2
JPH0579176B2 JP23288386A JP23288386A JPH0579176B2 JP H0579176 B2 JPH0579176 B2 JP H0579176B2 JP 23288386 A JP23288386 A JP 23288386A JP 23288386 A JP23288386 A JP 23288386A JP H0579176 B2 JPH0579176 B2 JP H0579176B2
Authority
JP
Japan
Prior art keywords
frame
wiring board
printed wiring
shaped
solid state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23288386A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6386462A (ja
Inventor
Susumu Fujiwara
Hiroyuki Yamamoto
Hajime Deguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP61232883A priority Critical patent/JPS6386462A/ja
Publication of JPS6386462A publication Critical patent/JPS6386462A/ja
Publication of JPH0579176B2 publication Critical patent/JPH0579176B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP61232883A 1986-09-29 1986-09-29 ソリツド・ステ−ト・リレ−の製造方法 Granted JPS6386462A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61232883A JPS6386462A (ja) 1986-09-29 1986-09-29 ソリツド・ステ−ト・リレ−の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61232883A JPS6386462A (ja) 1986-09-29 1986-09-29 ソリツド・ステ−ト・リレ−の製造方法

Publications (2)

Publication Number Publication Date
JPS6386462A JPS6386462A (ja) 1988-04-16
JPH0579176B2 true JPH0579176B2 (en]) 1993-11-01

Family

ID=16946333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61232883A Granted JPS6386462A (ja) 1986-09-29 1986-09-29 ソリツド・ステ−ト・リレ−の製造方法

Country Status (1)

Country Link
JP (1) JPS6386462A (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2078171B1 (es) * 1993-12-28 1998-01-16 Smartpack Tecnologia S A Procedimiento de fabricacion de modulos de potencia con elementos semiconductores.
JP7240148B2 (ja) 2018-11-21 2023-03-15 株式会社東芝 光結合装置

Also Published As

Publication number Publication date
JPS6386462A (ja) 1988-04-16

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term